others - 在Verilog中,BCD加法器求和

我试图在Verilog中编写一个BCD加法器,有一个模块有问题,下面是Verilog代码:


module DIGITADD(


 input [3:0] IN_A,


 input [3:0] IN_B,


 input CIN,


 output reg COUT,


 output reg [3:0] SUM


);



wire s2, c2;



always @ ( * ) 


begin


 assign {c2, s2} = IN_A + IN_B + CIN;



 if(s2 <= 9 && c2 == 0) begin


 assign {COUT, SUM} = {c2, s2};


 end


 else if({c2, s2} > 9) begin


 assign {COUT, SUM} = {c2, s2 + 6};


 end


end


endmodule



无论如何,当我尝试在Xilinx中进行合成时,出现以下错误:

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire'c2'is not a legal reg or variable lvalue

ERROR:HDLCompilers:247 - "DIGITADD.v" line 33 Reference to scalar wire's2'is not a legal reg or variable lvalue

ERROR:HDLCompilers:42 - "DIGITADD.v" line 33 Illegal left hand side of procedural assign

时间:

正确的代码如下,


module DIGITADD(


 input [3:0] IN_A,


 input [3:0] IN_B,


 input CIN,


 output COUT,


 output [3:0] SUM


 );



reg [4:0] s2;



assign SUM = s2[3:0];


assign COUT = s2[4];



always @ ( * )


begin


 s2 = IN_A + IN_B + CIN;


 if (s2 > 9)


 begin


 s2 = s2 + 6;


 end


end


endmodule 



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